1. Field of the Invention
The present invention is directed to an electrical circuit with a testing device for testing electrical connections in the electrical circuit. The invention is also directed to an electrical component having such an electrical circuit in integrated form. The present invention is also directed to a method for testing the quality of electrical connections in electrical circuits.
2. Description of the Related Art
It is known to test the quality of the connections of electronic assemblies with an in-circuit tester. An external tester is thereby connected to the assembly or assemblies under test with a needle bed adapted. Needles are mechanically positioned to measuring pointsxe2x80x94called measuring padsxe2x80x94that are already provided on the circuit. The testing points or, respectively, components are selected and provided with defined voltage levels via these mechanically placed and electrically driven needles. Faults are recognized by measuring and comparing the voltages at the output side of the measuring points to anticipated values.
These known testing methods have the disadvantage that the number of test pads to be separately provided increases greatly with the number of planned tests and the number of assemblies to be selected for a test. This particularly impedes the desired integration and high density of the assemblies on a printed circuit board. A needle mechanically placed onto a measuring point (test pad) requires a certain minimum size, since mechanical tolerances and the cost outlay for continued miniaturization must be taken into consideration. Special components, for example, components provided with cooling members, or large-scale integrated components having several 100 pins can therefore not be measured due to the limited space on the motherboard.
Given modern ball grid array (BGA) components that are characterized in that all connections to the printed circuit board are located under the component, it is practically impossible to provide test pads for all of these terminals without in turn destroying the advantages of this space-saving structure.
Furthermore, a mechanically high-precision and expensive needle bed adapter must be fabricated for each motherboard and must usually also be fabricated for different tests on the same motherboard. The fabrication takes a long time; this delays the development of a circuit, and the needle bed adapter is itself susceptible to malfunction.
It is also known to test circuits with a boundary scan test. Given this, a part of the test logic is integrated into the component. The basic idea is to insert a boundary scan cell as part of the integrated circuit itself between each pin terminal and the actual integrated circuit. A transmitter cell and a receiver cell is thereby needed for testing a connection. During the normal operating condition, the boundary scan cell transmits the received values from the input to the output. In the test mode, it reads the input value out and outputs a selectable test value at the output. All boundary cell scan test cells are connected to one another by a test bus. The data are connected on an external tester via this test bus during the test. The test bus standardized according to IEEE 1149.1 enables the test control and the data exchange.
What is disadvantageous about this Prior Art is that the method is dependent on external testing devices due to the extremely high calculating performance. Many test vectors are needed, i.e., sets of test values to be applied to the measuring points, with which, for example, a specific command is communicated to the circuit under test. As a result, a vector for the resulting values in turn is produced at the pins. In order to test the correct connections of the components to the printed circuit board, the functionality of specific elements and assemblies must be tested. To this end, however, many test vectors must be utilized and the result vectors that are obtained must be compared to the anticipated values. The external testing equipment must therefore provide a considerable calculating capacity; a separate computer is usually utilized for this purpose. Furthermore, when the results do not agree with the anticipated values, the result vectors usually contain little, if any, information about the nature of the fault.
None of the known testing devices can be completely integrated into a component in order to test electrical connections in the circuit in which they are employed. The quality of the connection can only be determined after a higher-ranking comparison, to which the values must be output and that usually does not take place on the electrical circuit itself but in one of the aforementioned external testing devices.
Consequently, it is not possible (or is possible only with significant expenditure) to integrate self-tests into the circuits. But this integration will be required for future assemblies and circuits.
As a self-test (during the service life) of a circuit, the implementation of a logic test has been previously known, by which a xe2x80x9cprogramxe2x80x9d is run in agreement with the normal function and, for the anticipated, xe2x80x9ccorrectxe2x80x9d results, it is assumed that the circuit is okay overall.
In addition, it is also known to find interruptions in transmission lines such as coaxial lines in that a signal is reflected at the fault location and the point of the interruption is determined from the signal propagation time.
The invention is therefore based on the object of offering an electrical circuit that does not require any external testing equipment for testing the quality of electrical connections on the circuit and that nonetheless enables a determination of the quality of the electrical connections in a simple way. A further object of the present invention is to offer a corresponding method for testing the quality of electrical connections in electrical circuits.
The above-described object is inventively achieved by an electrical circuit comprising a testing device for testing electrical connections quality in the electrical circuit, a test signal generator for generating a test signal and supplying the generated test signal to an electrical connection to be tested, an evaluator for receiving a reply signal from the connection under test in response to a supplied the test signal, the evaluator being configured for registering a propagation time between test signal and reply signal, and comparing the reply signal to an anticipated signal, and evaluating a quality of the tested electrical connection on a basis of the propagation time and the signal comparison.
The object of the invention is also achieved by a method for testing a quality of electrical connections in electrical circuits, comprising the steps of generating a defined test signal, supplying the generated test signal to an electrical connection to be tested, receiving a reply signal from the connection under test in response to the supplied test signal, determining a propagation time between the test signal and the reply signal; and comparing the reply signal to an anticipated signal for evaluating a quality of the electrical connection.
The inventive electrical circuit comprises a testing device composed of a test signal generator for generating a test signal and supplying this test signal to an electrical connection to be tested.
Furthermore, an evaluator is provided for the reception of a reply signal to a supplied test signal by the connection to be tested, by which the evaluator registers the propagation time between a test signal and a reply signal, compares the reply signal to an anticipated signal, and evaluates the quality of the tested electrical connection on the basis of the propagation time and of the signal comparison.
Advantageously, the effect of the modification of an electrical signal or pulse during the signal run that is otherwise undesired in digital circuits is precisely what is used. What is exploited is the fact that electrical connections are not ideal and one can only approximately assume an ideal transmission that does not change the shape of the signal. Capacitative, inductive, attenuating and reflective influences occur. Contrary to the previous opinion of the art that accorded no informational content to these changes of the digital signals and attempted to prevent the signal from changing over the propagation time, it is precisely these signal changes during operation of digital circuits that are inventively interpreted. The image of the reply signal is typical of the traversed path. When the test signal is observed, for example a square-wave signal resolved into its wave functions, the reply signal contains information about the characteristic impedance that the test signal experienced on the electrical connection under test.
It is also advantageous when the test signal generator supplies the test signal to the same end of the electrical connection under test at which the evaluator receives the reply signal. As a result of this, the signal reflected by the electrical circuit at the end of the electrical connection under test or by a preceding fault can be received as reply signal. This makes it possible to concentrate all of the components needed for the electrical circuit with testing device of the species described here in compact fashion at one location. In particular, these can be concentrated in an integrated circuit on a component.
It is also advantageous to fashion the electrical circuit such that the test signal generator generates a test signal having a signal width tab, so that the length over which the test signal runs on the connection under test at the appertaining wavelength xcex≈2tabxc3x97Vp is greater than approximately xcex/2. The test signal is thereby viewed as half-wave of a periodic signal. The typical propagation velocity of an electrical signal in a digital circuit is set as Vp.
Standard propagation velocities in digital circuits are approximately 60%-70% of the speed of light. The value Vp is thus set at approximately 60 percent of the speed of light or to a value corresponding to the circuit on a case-by-case basis.
A test of the above-described type can be especially favorably realized when this signal width is downwardly transgressed. According to the theory relating to long lines, the length of the line via which the test signal runs is to be taken into consideration under these conditions. The error occurring as a result thereof for the case of normal operation of a digital circuit can then no longer be neglected. Since the test given the inventive testing device is based on the principle of modifying the test signal, it is advantageous to adapt the signal width to this propagation time condition. It is also beneficial to add a safety margin of 100% to this condition insofar as possible and to then set the running length of the test signal greater than xcex in order to assure the applicability of the theory of the long line in any case.
A technically beneficial solution is to lengthen the propagation time of the test signal on the electrical connection under test in that a delay element is connected between test signal generator and connection under test. This delay elementxe2x80x94given a test signal with a signal width tab generated by the test signal generatorxe2x80x94lengthens the propagation time of the test signal over the electrical connection under test such that the apparent length over which the test signal runs on the connection under test is greater than approximately xcex/2 at the appertaining wavelength xcex≈2tabxc3x97Vp.
The condition beneficial for the testing device disclosed here, to the extent that the laws of the long line can be applied, can also be achieved when the test signal generator generates a test signal with a signal rise time tr, defined as the time span in which the signal rises from 10% of its value to 90% of its value, so that the propagation time of the test signal over the electrical connection under test is greater than approximately tr.
Just as in the above-described embodiments, it is also beneficial here to also add a safety margin of 100% to this condition insofar as possible and to then set the propagation time of the signal greater than 2tr. The signal rise time is thus short in comparison to the test signal propagation time over the electrical connection under test.
This advantage is also achieved in that a delay element is connected between test signal generator and connection under test. This delay elementxe2x80x94given a test signal with a signal rise time trxe2x80x94defined as time span in which the signal value rises from approximately 10% of its value to 90% of its valuexe2x80x94is generated by the test signal generator and lengthens the propagation time of the test signal over the electrical connection under test to more than tr.
In the above-described embodiments, standard pulses can also be advantageously employed as the test signal without having to provide complicated and expensive components for especially fast signal rise times or short signal widths. Since the effect of a lengthening of the propagation time of a signal is not desired in normal operation for a digital circuit, since errors occur as a result of such a lengthening and the working speed of the circuit is reduced, this only occurs when the circuit with the electrical connections to be tested is in the test mode. Only then is a delay element connected between the electrical connection under test, for example, the pin of an integrated component and the test signal generator or, respectively, evaluator.
Advantageously, the evaluator defines a maximum value of the reply signal, checks whether the maximum value of the reply signal lies within a time span t1 through t2, and then compares the reply signal to the anticipated signal. The limitation to the definition of the maximum value and the determination as to whether this lies in a time window of an anticipated reply signal simplifies the evaluation. The complete signal image need not be acquired. Above all, the signal need not be sampled, which would being very involved according to the sampling theorem. Potential other signals that do not derive from the test signal are filtered out by a time limitation mechanism, for example a gate circuit.
For determining the maximum value, the evaluator can compare the reply signal to reference voltage in analog fashion and store a value (e.g., a xe2x80x9c1xe2x80x9d, in a latch for every exceeded reference voltage), and can then convert these values into a data word of a specific width in a decoder. The reply signal is thus first quantized analog and then converted into a thermometer/digital code. Even when a specific value is only exceeded once, a xe2x80x9c1xe2x80x9d is set for the value in the latch. Accordingly, a series with values xe2x80x9c1xe2x80x9d reside in the latch after the measuring time up to the value that corresponds to the maximum value, otherwise values xe2x80x9c0xe2x80x9d result.
A decoder can then convert this thermometer/digital code into a standard digital value having a specific word width. It is advantageous that the determination of the maximum value is fast and does not cause any calculating outlay since only the maximum value is acquired.
Beneficially, the evaluator can compare the maximum value of the reply signal to an anticipated value upon allowance of a tolerance and thus evaluate the quality of the electrical connection. The evaluation of the reply signal ultimately ensues by an analysis of the reflection coefficient P. This is defined here as a ratio of the test signal maximum to the reply signal maximum. Which value is present for P is ultimately tested by prescribing an anticipated value for the maximum value of the reply signal. The actual comparison can ensue, for example, by forming a digital value having a specific bit width from the analog value and comparison to a likewise digitalized, anticipated value. Since a number of errors are conditioned by the analog-to-digital conversion, exact agreements of maximum value and anticipated value cannot be achieved in the comparison of the encoded measured values. A defined tolerance is therefore provided in that, for example, a specific plurality of last bits is left out of consideration in the comparison of the code words. A tolerance is also allowed given some other, standard type of comparison in order to take scatter and measuring imprecision into consideration. Since the reflection of the test signal at the end of the electrical connection under test is essentially dependent on the terminating impedance, the comparison of the maximum value of the reply signal to the anticipated value and, thus, the test for a specific value of P advantageously allows statements not only about the existence of a fault but, in case of a fault, also about the nature of the fault to a certain extent when significant values are interrogated as anticipated values for specific faults. The terminating impedance of an electrical connection anticipated in the xe2x80x9cgoodxe2x80x9d case is unambiguously defined for the circuit when this itself is in a specific, defined condition. By way of example, thus, a defined input impedance is expected for a specific input of a component with an integrated circuit when this is located at the end of the connection under test and when the component is in a defined condition.
Furthermore, the evaluator can compare the maximum value of the reply signal to the negative maximum value of the test signal as an anticipated value and thereby recognize an electrical connection to ground as being a proper condition and a faulty connection as a short to ground. Another advantageous simplification of the testing device derives as a result thereof. A check is carried out to see whether the value P≈xe2x88x921 is present. A connection to ground (GND) is established for the xe2x80x9cgoodxe2x80x9d case. When a fault has already been detected, the test for this value can recognize the short of this connection to ground (being stuck at 0). It is advantageous that this xe2x80x9cgoodxe2x80x9d case and the described fault can be determined without a significant calculation and simulation of the circuit.
Advantageously, the evaluator can compare the maximum value of the reply signal to zero and thereby recognize an electrical connection to another component with suitable input impedance as a proper condition and a faulty connection to another component with high-impedance input as shorted to another electrical connection when the nature of the fault is analyzed after a detected fault.
The evaluator can compare the maximum value of the reply signal to the positive maximum value of the test signal as an anticipated value and thereby recognize an electrical connection to an open terminal as being in a proper condition and a faulty connection as being interrupted.
Inventively, a test controller can be provided that collects the test results and outputs them via an interface.
Furthermore, according to the invention, an electrical component with an integrated circuit is provided that comprises an integrated circuit with an above-described electrical circuit. The analysis of potential faults can thus ensue on every component with integrated circuit itself. What is also beneficial compared to previously known embodiments of the Prior Art is that the necessary calculating power and the logistic outlay are reduced. The terminals of a component (e.g., an IC) can be checked in this way for correct connections without external registers or mechanical adaptation. For an electrical circuit with testing device disclosed here, no higher-ranking comparison of the values of the individual components of an electrical circuit is necessary.
This component can be beneficially implemented in that all terminals (pins) of the component for the connection of further components are connected star-like (in a star configuration) to a single test signal generator and the test signal generator successively supplies the terminals with a test signal, and all terminals are likewise connected star-like (in a star configuration) to a single evaluator that successively receives the reply signals.
Advantageously, potentially existing boundary scan cells according to the JTAG standard can conduct the test signal to the connections under test, where these cells are expanded by two drivers.
It is beneficial to implement an electrical component of the above-described species with an electrical circuit with a test controller that collects the test results and outputs them via an interface, as described above, such that the test controller present, given a test architecture according to the boundary scan method, outputs the test results, and the control command set of the test controller is expanded by a command to output the test results. A number of versions of this embodiment can be implemented. Thus, it is possible to implement the test controller on the electrical circuit integrated in the component. However, it is also possible to provide the test controller in the overall electrical circuit in which the component is utilized. As a result of this, it is possible to output the results of the tests in a plurality of components of the above-described species with the assistance of one test controller.
According to the invention, a method for testing the quality of electrical connections in electrical circuits is also provided.
A test signal is generated first in this method and is supplied to an electrical connection under test. A reply signal to a supplied test signal is then received from the connection under test; the propagation time between test signal and reply signal is then determined. The reply signal is compared to the anticipated signal in order to evaluate the quality of the electrical connection.
Beneficially, the test signal is supplied at the same end of the electrical connection under test at which the reply signal is received. As a result, the reflected signal can be received as described above on the basis of the electrical circuit.
A test signal having a signal width tab can be employed, so that the length over which the test signal runs on the connection under test at the appertaining wavelength xcex is greater than approximately xcex/2.
The propagation time of the test signal over the electrical connection under test is beneficially lengthened such that the apparent length over which the test signal runs on the connection under test is greater than approximately xcex/2 at the appertaining wavelength xcex. As described for the electrical circuit, standard methods of signal generation can thus be applied without particular effort.
The test signal can have a signal rise time tr, defined as time span in which the signal rises from 10% of its value to 90% of its value, so that the propagation time of the test signal over the electrical connection under test is greater than approximately tr.
The propagation time of the test signal over the electrical connection under test can be lengthened such that, given a signal rise time tr, defined as time span in which the signal rises from 10% of its value to 90% of its value, the propagation time is greater than approximately tr.
Beneficially, the maximum value of the reply signal is determined, and a check is carried out to see whether the maximum value of the reply signal lies within a time span t1 through t2, and the reply signal is then compared to the anticipated value.
For determining the maximum value of the reply signal, the reply signal can be compared to reference voltages in analog fashion and a value can be stored in a latch for every exceeded reference voltage, and these values can then be converted into a data word of a specific width in a decoder.
The maximum value of the reply signal can be compared to an anticipated value upon allowance of a tolerance, and the quality of the electrical connection can thus be evaluated.
Advantageously, the maximum value of the reply signal is compared to the negative maximum value of the test signal as an anticipated value and an electrical connection to ground is thereby recognized as being a proper condition and a faulty connection is recognized as a short to ground.
The maximum value of the reply signal can be compared to zero and an electrical connection to another component with suitable input impedance can be recognized as a proper condition and another connection to a component with a high-impedance input can be recognized as shorted to another electrical connection.
The maximum value of the reply signal can be compared to the positive maximum value of the test signal as an anticipated value, and an electrical connection to an open terminal can thereby be recognized as being a proper condition and another connection can be recognized as interrupted.
Furthermore, with an integrated component, a test signal from a single test signal generator can be successively supplied to all of its electrical connections to be tested to some other electrical circuit, to the pins, whereby the reply signals are successively received and evaluated in a single evaluator.
Finally, a test controller can be offered and the test results can be collected via the test controller and be output via an interface.
The invention is now explained in greater detail on the basis of an exemplary embodiment of an electrical circuit integrated in an electrical component. An embodiment with test controller given a simultaneously existing boundary scan test architecture is shown.